Browsing by Keywords "Integer linear programming"

Now showing items 1-7 of 7

    • Application mapping algorithms for mesh-based network-on-chip architectures 

      Tosun, S.; Ozturk, O.; Ozkan, E.; Ozen, M. (Springer New York LLC, 2015-03)
      Due to shrinking technology sizes, more and more processing elements and memory blocks are being integrated on a single die. However, traditional communication infrastructures (e.g., bus or point-to-point) cannot handle ...

    • Code scheduling for optimizing parallelism and data locality 

      Yemliha, T.; Kandemir, M.; Öztürk, Özcan; Kultursay, E.; Muralidhara, S. P. (Springer, 2010-08-09)
      As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. ...

    • Codon optimization by 0-1 linear programming 

      Arbib, C.; Pınar, Mustafa Ç.; Rossi, F.; Tessitore, A. (Elsevier, 2020-02)
      The problem of choosing an optimal codon sequence arises when synthetic protein-coding genes are added to cloning vectors for expression within a non-native host organism: to maximize yield, the chosen codons should have ...

    • Constrained min-cut replication for K-way hypergraph partitioning 

      Yazici V.; Aykanat, Cevdet (Institute for Operations Research and the Management Sciences (I N F O R M S), 2014)
      Replication is a widely-used technique in information retrieval and database systems for providing fault tolerance and reducing parallelization and processing costs. Combinatorial models based on hypergraph partitioning ...

    • Heterogeneous network-on-chip design through evolutionary computing 

      Ozturk, O.; Demirbas, D. (Taylor & Francis, 2010)
      This article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor ...

    • On-chip memory space partitioning for chip multiprocessors using polyhedral algebra 

      Ozturk, O.; Kandemir, M.; Irwin, M. J. (The Institution of Engineering and Technology, 2010)
      One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the ...

    • Robust path design algorithms for traffic engineering with restoration in MPLS networks 

      Yetginer, Emre; Karasan, Ezhan (IEEE, 2002-07)
      In this paper we study traffic engineering of restorable paths in multiprotocol label switching (MPLS) networks. We consider off-line computation of working and restoration paths with path rerouting as the restoration ...