Now showing items 1-4 of 4

    • Graph analytics accelerators for cognitive systems 

      Ozdal, M. M.; Yesil, S.; Kim, T.; Ayupov, A.; Greth, J.; Burns, S.; Ozturk, O. (Institute of Electrical and Electronics Engineers, 2017)
      Hardware accelerators are known to be performance and power efficient. This article focuses on accelerator design for graph analytics applications, which are commonly used kernels for cognitive systems. The authors propose ...
    • Hardware accelerator design for data centers 

      Yesil, S.; Ozdal, M. M.; Kim, T.; Ayupov, A.; Burns, S.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2016)
      As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized application-specific accelerators are becoming integral ...
    • JPEG hardware accelerator design for FPGA 

      Duman, Kaan; Çoǧun, Fuat; Öktem, L. (IEEE, 2007)
      A fully pipelined JPEG hardware accelerator that runs on FPGA is presented. The accelerator is designed interactively in a simulation environment, using a DSP hardware design automation tool chain. The encoder part of the ...
    • Source-to-source transformation based methodology for graph-parallel FPGA accelerators 

      Akyol, Cemil Kaan (Bilkent University, 2019-08)
      Graph applications are becoming more and more important with their widespread usage and the amounts of data they deal with. Biological and social web graphs are well-known examples which show the importance of efficient ...