Now showing items 1-8 of 8

    • Adaptive digital predistortion for linearization of power amplifier 

      Şekerlisoy, Burak (Bilkent University, 2009)
      In most communication systems, power amplifiers are used to obtain high output power. The nonlinear characteristics of the power amplifier leads to the distortion of the output signal. This distortion affects the efficiency ...
    • Adaptive digital predistortion for power amplifier linearization 

      Aslan, Makbule Pehlivan (Bilkent University, 2008)
      High power amplification of linear modulation schemes which exhibit fluctuating envelopes, invariably leads to the generation of distortion and intermodulation products. In order to avoid these effects, maintaining both ...
    • Double binary turbo codes analysis and decoder implementation 

      Yılmaz, Özlem (Bilkent University, 2008)
      Classical Turbo Code presented in 1993 by Berrau et al. received great attention due to its near Shannon Limit decoding performance. Double Binary Circular Turbo Code is an improvement on Classical Turbo Code and widely ...
    • FPGA based implementation of IEEE 80211a physical layer 

      İnce, Mustafa (Bilkent University, 2010)
      Orthogonal Frequency Division Multiplexing (OFDM) is a multicarrier transmission technique, in which a single bitstream is transmitted over a large number of closely-spaced orthogonal subcarriers. It has been adopted for ...
    • An FPGA implementation architecture for decoding of polar codes 

      Pamuk, Alptekin (IEEE, 2011)
      Polar codes are a class of codes versatile enough to achieve the Shannon bound in a large array of source and channel coding problems. For that reason it is important to have efficient implementation architectures for polar ...
    • An fpga implementation of successive cancellation list decoding for polar codes 

      Süral, Altuğ (Bilkent University, 2016-01)
      Polar Codes are the rst asymptotically provably capacity achieving error correction codes under low complexity successive cancellation (SC) decoding for binary discrete memoryless symmetric channels. Although SC is a ...
    • Reconfigurable hardened latch and flip-flop for FPGAs 

      Ahangari, H.; Alouani, I.; Ozturk, O.; Niar, S. (IEEE Computer Society, 2017)
      In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices ...
    • Source-to-source transformation based methodology for graph-parallel FPGA accelerators 

      Akyol, Cemil Kaan (Bilkent University, 2019-08)
      Graph applications are becoming more and more important with their widespread usage and the amounts of data they deal with. Biological and social web graphs are well-known examples which show the importance of efficient ...