Browsing by Keywords "Energy delay product"
Now showing items 1-2 of 2
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High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model
(IEEE, 2016-05)In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and ... -
A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model
(IEEE, 2015-11)In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories ...
