Browsing by Keywords "Chip multiprocessors"
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Adaptive thread scheduling in chip multiprocessors
(Springer, 2019)The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems. We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule ... -
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
(Association for Computing Machinery, 2010-04)Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, programming them is even more challenging. As the ... -
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model
(IEEE, 2016-05)In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and ... -
Improving chip multiprocessor reliability through code replication
(Pergamon Press, 2010)Chip multiprocessors (CMPs) are promising candidates for the next generation computing platforms to utilize large numbers of gates and reduce the effects of high interconnect delays. One of the key challenges in CMP design ... -
Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy
(Elsevier BV, 2017)Management of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, ...
