Browsing by Keywords "Charge trapping"
Now showing items 1-9 of 9
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2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices
(IEEE, 2014-08)In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping memory devices is studied. Si-NPs are fabricated by laser ablation of a silicon wafer in deionized water followed by sonication ... -
Charge Trapping Memory with 2.85-nm Si-Nanoparticles Embedded in HfO2
(ECS, 2015-05)In this work, the effect of embedding 2.85-nm Si-nanoparticles charge trapping layer in between double layers of high-κ Al<inf>2</inf>O<inf>3</inf>/HfO<inf>2</inf> oxides is studied. Using high frequency (1 MHz) ... -
Cubic-phase zirconia nano-island growth using atomic layer deposition and application in low-power charge-trapping nonvolatile-memory devices
(Institute of Physics Publishing Ltd., 2017)The manipulation of matter at the nanoscale enables the generation of properties in a material that would otherwise be challenging or impossible to realize in the bulk state. Here, we demonstrate growth of zirconia ... -
Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O3/HfO2 tunnel oxide
(Springer New York LLC, 2015)In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the ... -
Graphene Nanoplatelets Embedded in HfO2 for MOS Memory
(Electrochemical Society Inc., 2015)In this work, a MOS memory with graphene nanoplatelets charge trapping layer and a double layer high-κ Al<inf>2</inf>O<inf>3</inf>/HfO<inf>2</inf> tunnel oxide is demonstrated. Using C-V<inf>gate</inf> measurements, the ... -
Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission
(2014)A low power zinc-oxide (ZnO) charge trapping memory with embedded silicon (Si) nanoparticles is demonstrated. The charge trapping layer is formed by spin coating 2 nm silicon nanoparticles between Atomic Layer Deposited ... -
Memory effect by charging of ultra‐small 2‐nm laser‐synthesized solution processable Si‐nanoparticles embedded in Si–Al2O3–SiO2 structure
(Wiley-VCH Verlag, 2015)A memory structure containing ultra-small 2-nm laser-synthesized silicon nanoparticles is demonstrated. The Si-nanoparticles are embedded between an atomic layer deposited high-κ dielectric Al<inf>2</inf>O<inf>3</inf> layer ... -
Silicon nanoparticle charge trapping memory cell
(Wiley-VCH Verlag, 2014)A charge trapping memory with 2 nm silicon nanoparticles (Si NPs) is demonstrated. A zinc oxide (ZnO) active layer is deposited by atomic layer deposition (ALD), preceded by Al2O3 which acts as the gate, blocking and ... -
ZnO based charge trapping memory with embedded nanoparticles
(IEEE, 2012)A thin film ZnO charge trapping memory cell with embedded nanoparticles is demonstrated by Physics Based TCAD simulation. The results show 3V increase in the Vt shift due to the nanoparticles for the same operating voltage. ...
