Browsing by Keywords "Cache memory"
Now showing items 1-7 of 7
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Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table
(Association for Computing Machinery, Inc, 2016)Chip multiprocessors (CMPs) require effective cache coher-ence protocols as well as fast virtual-To-physical address trans-lation mechanisms for high performance. Directory-based cache coherence protocols are the ... -
NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories
(Institute of Electrical and Electronics Engineers Inc., 2016)Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to ... -
Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy
(Elsevier BV, 2017)Management of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, ... -
Optimizing shared cache behavior of chip multiprocessors
(2009)One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work ... -
Prefetch throttling and data pinning for improving performance of shared caches
(2008)In this paper, we (i) quantify the impact of compilerdirected I/O prefetching on shared caches at I/O nodes. The experimental data collected shows that while I/O prefetching brings some benefits, its effectiveness reduces ... -
Profiler and compiler assisted adaptive I/O prefetching for shared storage caches
(2008)I/O prefetching has been employed in the past as one of the mech- anisms to hide large disk latencies. However, I/O prefetching in parallel applications is problematic when multiple CPUs share the same set of disks due to ... -
Shared scratch pad memory space management across applications
(Inderscience Publishers, 2009)Scratch Pad Memories (SPMs) have received considerable attention lately as on-chip memory building blocks. The main characteristic that distinguishes an SPM from a conventional cache memory is that the data flow is controlled ...
