Browsing by Keywords "3D integration"
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Atomic Layer Deposition for Vertically Integrated ZnO Thin Film Transistors: Toward 3D High Packing Density Thin Film Electronics
(Wiley-VCH Verlag, 2017)We report on the first demonstration of the atomic layer deposition (ALD) based three dimensional (3D) integrated ZnO thin film transistors (TFTs) on rigid substrates. Devices exhibit high on-off ratio (∼106) and high ... -
OptMem: dark-silicon aware low latency hybrid memory design
(IEEE, 2016-01)In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static ... -
Temperature-aware core mapping for heterogeneous 3D NoC design through constraint programming
(Institute of Electrical and Electronics Engineers, 2020)In the context of Network-on-Chip (NoC) based Chip Multiprocessor (CMP) design, core mapping for application specific systems is a challenging problem. In such designs, various decisions have to be made that affect performance ...
