Browsing by Keywords "3D"

Now showing items 1-4 of 4

    • Energy reduction in 3D NoCs through communication optimization 

      Ozturk, O.; Akturk I.; Kadayif I.; Tosun, S. (Springer Wien, 2015)
      Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining ...

    • ILP-based communication reduction for heterogeneous 3D network-on-chips 

      Aktürk, İsmail; Öztürk, Özcan (IEEE, 2013-02-03)
      Network-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. ...

    • Reliability-aware 3D chip multiprocessor design 

      Öztürk, Özcan; Aktürk, İsmail (IEEE, 2012-06)
      Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit ...

    • Reliability-aware heterogeneous 3D chip multiprocessor design 

      Akturk, I.; Ozturk, O. (Springer, 2013)
      Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit ...