Now showing items 1-6 of 6

    • Optimizing shared cache behavior of chip multiprocessors 

      Kandemir, M.; Muralidhara, S. P.; Narayanan, S. H. K.; Zhang, Y.; Öztürk, Özcan (ACM, 2009-12)
      One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work ...
    • Process variation aware thread mapping for chip multiprocessors 

      Hong, S.; Narayanan, S. H. K.; Kandemir, M.; Özturk, Özcan (IEEE, 2009-04)
      With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that ...
    • A scratch-pad memory aware dynamic loop scheduling algorithm 

      Öztürk, Özcan; Kandemir, M.; Narayanan, S. H. K. (IEEE, 2008-03)
      Executing array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, ...
    • Slicing based code parallelization for minimizing inter-processor communication 

      Kandemir, M.; Zhang, Y.; Muralidhara, S. P.; Öztürk, Özcan; Narayanan, S. H. K. (ACM, 2009-10)
      One of the critical problems in distributed memory multi-core architectures is scalable parallelization that minimizes inter-processor communication. Using the concept of iteration space slicing, this paper presents a new ...
    • Workload clustering for increasing energy savings on embedded MPSOCS 

      Öztürk, Özcan; Kandemir, M.; Narayanan, S. H. K. (Wiley, 2012)
      Our goal in this chapter is to explore a workload (job) clustering scheme that combines voltage scaling with processor shutdown.1 The uniqueness of the proposed unified approach is that it maximizes the opportunities for ...
    • Workload clustering for increasing energy savings on embedded MPSOCS 

      Ozturk, O.; Kandemir, M.; Narayanan, S. H. K. (John Wiley and Sons, 2012)
      Voltage/frequency scaling andprocessor low-power modes (i.e., processor shut-down) are two important mechanisms usedfor reducing energy consumption in embedded MPSoCs. While a unified scheme that combines these two ...