Browsing by Author "Kandemir, M."

Now showing items 1-20 of 24

    • Access pattern-based code compression for memory-constrained systems 

      Ozturk, O.; Kandemir, M.; Chen, G. (Association for Computing Machinery, 2008-09)
      As compared to a large spectrum of performance optimizations, relatively less effort has been dedicated to optimize other aspects of embedded applications such as memory space requirements, power, real-time predictability, ...

    • Adaptive prefetching for shared cache based chip multiprocessors 

      Kandemir, M.; Zhang, Y.; Öztürk, Özcan (IEEE, 2009-04)
      Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based CMP, multiple cores compete for the shared on-chip ...

    • Automatic segmentation of colon glands using object-graphs 

      Gunduz Demir, C.; Kandemir, M.; Tosun, A. B.; Sokmensuer, C. (Elsevier BV, 2010)
      Gland segmentation is an important step to automate the analysis of biopsies that contain glandular structures. However, this remains a challenging problem as the variation in staining, fixation, and sectioning procedures ...

    • A cache topology-aware multi-query scheduler for multicore architectures 

      Orhan, U.; Ding, W.; Yedlapalli, P.; Kandemir, M.; Öztürk, Özcan (IEEE, 2014)
      Growing performance gap between processors and main memory has made it worthwhile to consider off-chip data accesses in multi-query processing [2], [1], [3]. Exploiting data-sharing opportunities among concurrent queries ...

    • Code scheduling for optimizing parallelism and data locality 

      Yemliha, T.; Kandemir, M.; Öztürk, Özcan; Kultursay, E.; Muralidhara, S. P. (Springer, 2010-08-09)
      As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. ...

    • Compiler directed network-on-chip reliability enhancement for chip multiprocessors 

      Ozturk, O.; Kandemir, M.; Irwin, M. J.; Narayanan, S.H. K. (Association for Computing Machinery, 2010-04)
      Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, programming them is even more challenging. As the ...

    • Compiler-directed energy reduction using dynamic voltage scaling and voltage islands for embedded systems 

      Ozturk, O.; Kandemir, M.; Chen G. (Institute of Electrical and Electronics Engineers, 2013)
      Addressing power and energy consumption related issues early in the system design flow ensures good design and minimizes iterations for faster turnaround time. In particular, optimizations at software level, e.g., those ...

    • Dynamic thread and data mapping for NoC based CMPs 

      Kandemir, M.; Öztürk, Özcan; Muralidhara, S. P. (IEEE, 2009-07)
      Thread mapping and data mapping are two important problems in the context of NoC (network-on-chip) based CMPs (chip multiprocessors). While a compiler can determine suitable mappings for data and threads, such static ...

    • ILP-based energy minimization techniques for banked memories 

      Ozturk, O.; Kandemir, M. (Association for Computing Machinery, 2008-07)
      Main memories can consume a significant portion of overall energy in many data-intensive embedded applications. One way of reducing this energy consumption is banking, that is, dividing available memory space into multiple ...

    • Improving multicore system performance through data compression 

      Öztürk, Özcan; Kandemir, M. (Wiley, 2017)
      As applications become more and more complex, it is becoming extremely important to have sufficient compute power on the chip. Multicore and many-core systems have been introduced to address this problem. This chapter ...

    • Object-oriented texture analysis for the unsupervised segmentation of biopsy images for cancer detection 

      Tosun, A. B.; Kandemir, M.; Sokmensuer, C.; Gunduz Demir, C. (Elsevier BV, 2009-06)
      Staining methods routinely used in pathology lead to similar color distributions in the biologically different regions of histopathological images. This causes problems in image segmentation for the quantitative analysis ...

    • On-chip memory space partitioning for chip multiprocessors using polyhedral algebra 

      Ozturk, O.; Kandemir, M.; Irwin, M. J. (The Institution of Engineering and Technology, 2010)
      One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the ...

    • Optimizing shared cache behavior of chip multiprocessors 

      Kandemir, M.; Muralidhara, S. P.; Narayanan, S. H. K.; Zhang, Y.; Öztürk, Özcan (ACM, 2009-12)
      One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work ...

    • Prefetch throttling and data pinning for improving performance of shared caches 

      Öztürk, Özcan.; Son, S. W.; Kandemir, M.; Karaköy, M. (IEEE, 2008-11)
      In this paper, we (i) quantify the impact of compilerdirected I/O prefetching on shared caches at I/O nodes. The experimental data collected shows that while I/O prefetching brings some benefits, its effectiveness reduces ...

    • Process variation aware thread mapping for chip multiprocessors 

      Hong, S.; Narayanan, S. H. K.; Kandemir, M.; Özturk, Özcan (IEEE, 2009-04)
      With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that ...

    • Profiler and compiler assisted adaptive I/O prefetching for shared storage caches 

      Son, S. W.; Kandemir, M.; Kolcu, I.; Muralidhara, S. P.; Öztürk, Öztürk; Karakoy, M. (ACM, 2008-10)
      I/O prefetching has been employed in the past as one of the mech- anisms to hide large disk latencies. However, I/O prefetching in parallel applications is problematic when multiple CPUs share the same set of disks due to ...

    • A scratch-pad memory aware dynamic loop scheduling algorithm 

      Öztürk, Özcan; Kandemir, M.; Narayanan, S. H. K. (IEEE, 2008-03)
      Executing array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, ...

    • Shared scratch pad memory space management across applications 

      Ozturk, Ozcan; Kandemir, M.; Son, S. W.; Kolcu, I. (Inderscience Publishers, 2009)
      Scratch Pad Memories (SPMs) have received considerable attention lately as on-chip memory building blocks. The main characteristic that distinguishes an SPM from a conventional cache memory is that the data flow is controlled ...

    • Slicing based code parallelization for minimizing inter-processor communication 

      Kandemir, M.; Zhang, Y.; Muralidhara, S. P.; Öztürk, Özcan; Narayanan, S. H. K. (ACM, 2009-10)
      One of the critical problems in distributed memory multi-core architectures is scalable parallelization that minimizes inter-processor communication. Using the concept of iteration space slicing, this paper presents a new ...

    • SPM management using markov chain based data access prediction 

      Yemliha, T.; Srikantaiah, S.; Kandemir, M.; Öztürk, Özcan (IEEE, 2008-11)
      Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular accesses like scalar values and array expressions ...