Now showing items 1-20 of 44

    • Adaptive compute-phase prediction and thread prioritization to mitigate memory access latency 

      Aktürk, İsmail; Öztürk, Özcan (ACM, 2014-06)
      The full potential of chip multiprocessors remains unex- ploited due to the thread oblivious memory access sched- ulers used in off-chip main memory controllers. This is especially pronounced in embedded systems due to ...
    • Adaptive prefetching for shared cache based chip multiprocessors 

      Kandemir, M.; Zhang, Y.; Öztürk, Özcan (IEEE, 2009-04)
      Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based CMP, multiple cores compete for the shared on-chip ...
    • Adaptive routing framework for network on chip architectures 

      Mustafa, Naveed Ul; Öztürk, Özcan; Niar, S. (ACM, 2016-01)
      In this paper we suggest and demonstrate the idea of applying multiple routing algorithms during the execution of a real application mapped on a Network-on-Chip (NoC). Traffic pattern of a real application may change during ...
    • Adaptive thread scheduling in chip multiprocessors 

      Aktürk, İ.; Öztürk, Özcan (Springer, 2019)
      The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems. We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule ...
    • Analysis of design parameters in safety-critical computers 

      Ahangari, Hamzeh; Atik, Funda; Özkök, Y. İ.; Yıldırım, A.; Ata, S. O.; Öztürk, Özcan (IEEE, 2020)
      Nowadays, safety-critical computers are extensively used in many civil domains like transportation including railways, avionics, and automotive. In evaluating these safety critical systems, previous studies considered ...
    • Analysis of design parameters in SIL-4 safety-critical computer 

      Ahangari, Hamzeh; Özkök, Y. I.; Yıldırım, A.; Say, F.; Atik, Funda; Öztürk, Özcan (IEEE, 2017-01)
      Nowadays, Safety-critical computers are extensively used in may civil domains like transportation including railways, avionics and automotive. We noticed that in design of some previous works, some critical safety design ...
    • Architectural requirements for energy efficient execution of graph analytics applications 

      Özdal, Muhammet Mustafa; Yeşil, Şerif; Kim, T.; Ayupov, A.; Burns, S.; Öztürk, Özcan (IEEE, 2015-11)
      Intelligent data analysis has become more important in the last decade especially because of the significant increase in the size and availability of data. In this paper, we focus on the common execution models and ...
    • AutopaR: An Automatic Parallelization Tool for Recursive Calls 

      Kalender, Mert Emin; Mergenci, Cem; Öztürk, Özcan (IEEE, 2014-09)
      Manycore systems are becoming more and more powerful with the integration of hundreds of cores on a single chip. However, writing parallel programs on these manycore systems has become a problem since the amount of available ...
    • Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table 

      Soltaniyeh, M.; Kadayıf, I.; Öztürk, Özcan (ACM, 2016- 05)
      Chip multiprocessors (CMPs) require effective cache coher-ence protocols as well as fast virtual-To-physical address trans-lation mechanisms for high performance. Directory-based cache coherence protocols are the ...
    • Cache hierarchy-aware query mapping on emerging multicore architectures 

      Öztürk, Özcan; Orhan, U.; Ding, W.; Yedlapalli, P.; Kandemir, M. T. (IEEE, 2017)
      One of the important characteristics of emerging multicores/manycores is the existence of 'shared on-chip caches,' through which different threads/processes can share data (help each other) or displace each other's data ...
    • A cache topology-aware multi-query scheduler for multicore architectures 

      Orhan, U.; Ding, W.; Yedlapalli, P.; Kandemir, M.; Öztürk, Özcan (IEEE, 2014)
      Growing performance gap between processors and main memory has made it worthwhile to consider off-chip data accesses in multi-query processing [2], [1], [3]. Exploiting data-sharing opportunities among concurrent queries ...
    • Classifying data blocks at subpage granularity with an on-chip page table to improve coherence in tiled CMPs 

      Soltaniyeh, M.; Kadayif, I.; Öztürk, Özcan (Institute of Electrical and Electronics Engineers, 2018)
      As shown in some prior studies, a significant percentage of data blocks accessed in parallel codes are private, and not keeping track of those blocks can improve the effectiveness of directory structures in Chip multiprocessors ...
    • Code scheduling for optimizing parallelism and data locality 

      Yemliha, T.; Kandemir, M.; Öztürk, Özcan; Kultursay, E.; Muralidhara, S. P. (Springer, 2010-08-09)
      As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. ...
    • Dynamic thread and data mapping for NoC based CMPs 

      Kandemir, M.; Öztürk, Özcan; Muralidhara, S. P. (IEEE, 2009-07)
      Thread mapping and data mapping are two important problems in the context of NoC (network-on-chip) based CMPs (chip multiprocessors). While a compiler can determine suitable mappings for data and threads, such static ...
    • Effective kernel mapping for OpenCL applications in heterogeneous platforms 

      Albayrak, Ömer Erdil; Aktürk, İsmail; Öztürk, Özcan (Institute of Electrical and Electronics Engineers, 2012-09)
      Many core accelerators are being deployed in many systems to improve the processing capabilities. In such systems, application mapping need to be enhanced to maximize the utilization of the underlying architecture. Especially ...
    • Energy efficient architecture for graph analytics accelerators 

      Özdal, Muhammet Mustafa; Yeşil, Şerif; Kim, T.; Ayupov, A.; Greth, J.; Burns, S.; Öztürk, Özcan (IEEE, 2016-06)
      Specialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable ...
    • Exploiting architectural features of a computer vision platform towards reducing memory stalls 

      Mustafa, Naveed Ul; O’Riordan, M. J.; Rogers, S.; Öztürk, Özcan (Springer, 2020)
      Computer vision applications are becoming more and more popular in embedded systems such as drones, robots, tablets, and mobile devices. These applications are both compute and memory intensive, with memory bound stalls ...
    • Fault-tolerant irregular topology design method for network-on-chips 

      Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Öztürk, Özcan (IEEE, 2014)
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...
    • FPGA implementation of a fault-tolerant application-specific NoC design 

      Yeşil, Şerif; Tosun, S.; Öztürk, Özcan (IEEE, 2016-04)
      Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem ...
    • Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach 

      Onsori, Salman; Asad, A.; Öztürk, Özcan; Fathy, M. (IEEE, 2015-12)
      Energy consumption becomes the most critical limitation on the performance of nowadays embedded system designs. On-chip memories due to major contribution in overall system energy consumption are always significant issue ...