Browsing by Keywords "Multiprocessing systems"
Now showing items 1-20 of 21
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Adaptive prefetching for shared cache based chip multiprocessors
(IEEE, 2009-04)Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based CMP, multiple cores compete for the shared on-chip ... -
Application-specific heterogeneous network-on-chip design
(Oxford University Press, 2014)As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in ... -
Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table
(ACM, 2016- 05)Chip multiprocessors (CMPs) require effective cache coher-ence protocols as well as fast virtual-To-physical address trans-lation mechanisms for high performance. Directory-based cache coherence protocols are the ... -
Code scheduling for optimizing parallelism and data locality
(Springer, 2010-08-09)As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. ... -
Dynamic thread and data mapping for NoC based CMPs
(IEEE, 2009-07)Thread mapping and data mapping are two important problems in the context of NoC (network-on-chip) based CMPs (chip multiprocessors). While a compiler can determine suitable mappings for data and threads, such static ... -
Efficient fast hartley transform algorithms for hypercube-connected multicomputers
(IEEE, 1995)Although fast Hartley transform (FHT) provides efficient spectral analysis of real discrete signals, the literature that addresses the parallelization of FHT is extremely rare. FHT is a real transformation and does not ... -
Energy efficient architecture for graph analytics accelerators
(IEEE, 2016-06)Specialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable ... -
A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors
(IEEE, 2016-05)Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era cause a drastic increase in leakage power consumption and ... -
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model
(IEEE, 2016-05)In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and ... -
A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model
(IEEE, 2015-11)In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories ... -
Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach
(IEEE, 2015-12)Energy consumption becomes the most critical limitation on the performance of nowadays embedded system designs. On-chip memories due to major contribution in overall system energy consumption are always significant issue ... -
Multicore education through simulation
(IEEE, 2009-07)This paper presents the experiences using a commercial full system simulation platform - Simics - in a graduate Chip Multiprocessors class. The Simics platform enables students and researchers to do research on computer ... -
On-chip memory space partitioning for chip multiprocessors using polyhedral algebra
(The Institution of Engineering and Technology, 2010)One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the ... -
Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy
(Elsevier BV, 2017)Management of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, ... -
Optimizing shared cache behavior of chip multiprocessors
(ACM, 2009-12)One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work ... -
OptMem: dark-silicon aware low latency hybrid memory design
(IEEE, 2016-01)In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static ... -
PHR: A parallel hierarchical radiosity system with dynamic load balancing
(Springer, 2005)In this paper, we present a parallel system called PHR for computing hierarchical radiosity solutions of complex scenes. The system is targeted for multi-processor architectures with distributed memory. The system evaluates ... -
Process variation aware thread mapping for chip multiprocessors
(IEEE, 2009-04)With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that ... -
A scratch-pad memory aware dynamic loop scheduling algorithm
(IEEE, 2008-03)Executing array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, ... -
Shared scratch pad memory space management across applications
(Inderscience Publishers, 2009)Scratch Pad Memories (SPMs) have received considerable attention lately as on-chip memory building blocks. The main characteristic that distinguishes an SPM from a conventional cache memory is that the data flow is controlled ...
