Aykanat, CevdetÖzgü, ÖzlemGüven, N.2016-02-082016-02-081994http://hdl.handle.net/11693/27784Date of Conference: 12-14 April 1994Conference Name: 7th Mediterranean Electrotechnical Conference, MELECON 1994Vector processors have promised an enormous increase in computing speed for computationally intensive and time-critical power system problems which require the repeated solution of sparse linear equations. Due to short vectors processed in these applications, standard sparsity-based algorithms need to be restructured for efficient vectorization. This paper presents a novel data storage scheme and an efficient vectorization algorithm that exploits the intrinsic architectural features of vector computers such as sectioning and chaining. As the benchmark, the solution phase of the Fast Decoupled Load Flow algorithm is used in simulations. The relative performances of the proposed and existing vectorization schemes are evaluated, both theoretically and experimentally, on IBM 3090/VF.EnglishAlgorithmsComputer simulationData storage equipmentData structuresDigital arithmeticElectric power systemsMatrix algebraPipeline processing systemsProgram compilersVectorsFast decoupled load flowForward/backward substitutionsSparse linear equationsVector computerVectorizationComputer architectureConference Paper10.1109/MELCON.1994.380916