Mozammel, Amir2022-01-282022-01-282021-10-261549-7747http://hdl.handle.net/11693/76868( Early Access )This brief proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture uses a novel branch metric unit specific to PAC codes. The proposed decoder is tested on FPGA, and its performance is evaluated on ASIC using TSMC 28 nm 0.72 V library. The decoder can be clocked at 500 MHz and reach an average information throughput of 38 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128 and a code rate of 1/2.EnglishPAC codesSequential decodingFanoPolar codingVLSIArticle10.1109/TCSII.2021.31232701558-3791