Karsavuran, Mustafa Ozan2016-01-082016-01-082014http://hdl.handle.net/11693/18330Ankara : The Department of Computer Engineering and the Graduate School of Engineering and Science of Bilkent University, 2014.Thesis (Master's) -- Bilkent University, 2014.Includes bibliographical references leaves 44-48.Sparse matrix-vector and matrix-transpose-vector multiplications (Sparse AAT x) are the kernel operations used in iterative solvers. Sparsity pattern of the input matrix A, as well as its transpose, remains the same throughout the iterations. CPU cache could not be used properly during these Sparse AAT x operations due to irregular sparsity pattern of the matrix. We propose two parallelization strategies for Sparse AAT x. Our methods partition A matrix in order to exploit cache locality for matrix nonzeros and vector entries. We conduct experiments on the recently-released Intel R Xeon PhiTM coprocessor involving large variety of sparse matrices. Experimental results show that proposed methods achieve higher performance improvement than the state-of-the-art methods in the literature.x, 48 leaves, graphicsEnglishinfo:eu-repo/semantics/openAccessIntel Many Integrated Core Architecture (Intel MIC)Intel Xeon PhiCache LocalitySparse MatrixSparse Matrix-Vector MultiplicationSparse Matrix-Vector and Matrix-Transpose-Vector MultiplicationHypergraph ModelHypergraph PartitioningQA76.88 .K37 2014Computer architecture.High performance computing.Distributed shared memory.Computer programming.ThesisB148325