Demiriz, A.Ahangari, HamzehÖztürk, Özcan2021-03-032021-03-03202097817281658371066-6192http://hdl.handle.net/11693/75717Date of Conference: 11-13 March 2020Conference Name: 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020In the context of Network-on-Chip (NoC) based Chip Multiprocessor (CMP) design, core mapping for application specific systems is a challenging problem. In such designs, various decisions have to be made that affect performance and power consumption. Moreover, in emerging 3D NoC systems, by intensification of cooling issues, temperature constraints on hot-spots are added, and problem becomes more complicated. In this paper, an earlier Constraint Programming (CP) methodology for heterogeneous 2D NoC design is extended to 3D model, while critical temperature constraints are accounted. In a single-stage, our approach can choose core types from a set of low, medium and high power, and assign them to appropriate places on the mesh which minimizes the overall computation time and communication cost while satisfying the temperature constraints. To achieve our objective, in addition to cores placement problem, tasks should also be scheduled on corresponding cores with matching performance levels to minimize the overall completion time (makespan). Experimental results show that task completion times are more dependent on the mesh structure for our benchmark data. 3D mesh structures may yield shorter task completion times, without compromising thermal constraints. On the other hand, restricting the peak temperature naturally requires the usage of low-performance computing elements which inherently may delay the processing time.EnglishNetwork-on-chip3D integrationHeterogeneousCore mappingTask schedulingConstraint programmingConference Paper10.1109/PDP50117.2020.0005497817281658202377-5750