Aktürk, İ.Öztürk, Özcan2020-02-032020-02-0320190885-7458http://hdl.handle.net/11693/52984The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems. We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that inter-thread contention is minimized. A novel multi-metric scoring scheme is used which specifies L1 cache access characteristics of threads. Scheduling decisions are made based on these multi-metric scores of threads.EnglishAdaptive schedulingChip multiprocessorsInter-thread contentionMulti-metric scoringArticle10.1007/s10766-019-00637-y