Ozturk, OzcanKandemir, M.Son, S. W.Kolcu, I.2016-02-082016-02-0820091741-1068http://hdl.handle.net/11693/22665Scratch Pad Memories (SPMs) have received considerable attention lately as on-chip memory building blocks. The main characteristic that distinguishes an SPM from a conventional cache memory is that the data flow is controlled by software. The main focus of this paper is the management of an SPM space shared by multiple applications that can potentially share data. The proposed approach has three major components; a compiler analysis phase, a runtime space partitioner, and a local partitioning phase. Our experimental results show that the proposed approach leads to minimum completion time among all alternate memory partitioning schemes tested.EnglishChip multiprocessorBuilding blockChip multiprocessorCompiler analysisData flowMain characteristicsMemory space managementMinimum completion timeMultiple applicationsOn chip memoryParallel executionRuntimeScratch pad memoryMicroprocessor chipsMultiprocessing systemsSystems analysisCache memoryArticle10.1504/IJES.2009.0272401741-1076