High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model

Onsori, SalmanAsad, ArghavanRaahemifar, K.Fathy, M.2018-04-122018-04-122016-05http://hdl.handle.net/11693/37724Date of Conference: 22-25 May 2016Conference name: 2016 IEEE International Symposium on Circuits and Systems (ISCAS)In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D CMP compared to the Baseline memory design. © 2016 IEEE.EnglishConvex-optimizationDark siliconEmbedded chip-multiprocessor (eCMP)Hybrid memory architectureNon-volatile memory (NVM)Power managementConvex optimizationData storage equipmentDesignDigital storageEnergy utilizationMultiprocessing systemsOptimizationPower managementProduct designRandom access storageReconfigurable hardwareSiliconStatic random access storageChip multiprocessorsDark siliconsEmbedded chipsEnergy delay productNon-volatile memoryOptimization modelingProposed architecturesReduce energy consumptionMemory architectureHigh performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization modelConference Paper10.1109/ISCAS.2016.7539127