Hasan, T.Zafar, SalahuddinÖzbay, EkmelKashif, A. U.2023-02-282023-02-282022-05-16http://hdl.handle.net/11693/111881Conference Name: International Conf on Electrical and Electronic Engineering (ICEEE)Date of Conference: 29-31 March 2022An analysis has been made on high-K dielectrics (HfO 2 and ZrO 2) for the CMOS process up to 14 nm FAB technology node. The aim is to study the reduction in gate leakage current for Nano-scale devices. High-K Dielectric having K ≥ 20 is beneficial for CMOS Nano-devices, reducing the gate leakage current when EOT ≤ 0.5 nm. MOS structure with high-K, i.e., HfO 2 and ZrO 2 , has been simulated in SILVACO T-CAD to consider as gate stack: metal/oxide/p-Si for the different FAB nodes; 45, 32, 22 & 14 nm. SiO 2 is considered a reference to optimize the MOS structure with high-K dielectric. As a result, 7–8 times the higher physical gate oxide layer is achieved compared to SiO 2 , which has a significant impact on minimizing the gate leakage current.EnglishCMOSHigh-K dielectricE.O.TITRSFAB nodeTCADConference Paper10.1109/ICEEE55327.2022.9772574