Ahangari, HamzehAlouani, I.Öztürk, ÖzcanNiar, S.Rivenq, A.2018-04-122018-04-122016-04http://hdl.handle.net/11693/37751Date of Conference: 12-14 April 2016Conference name: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor pipeline, it is mandatory to enhance the RF reliability to develop fault tolerant architectures. This paper proposes Adjacent Register Hardened RF (ARH), a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening registers at runtime. Registers are paired together by some special switches referred to as joiners. Dummy sign bits of each register are used to keep redundant data of its counterpart register. We use 7T/14T SRAM cell [6] to combine redundant bits together to make a single bit cell which is, by far, more resilient against faults. Our simulations show that with 3% to 12% power overhead and 10% to 20% increase in area, in comparison to baseline RF, we can obtain up to 80% reduction in soft error rate (SER). © 2016 IEEE.English7T/14T SRAMNarrow-widthRegister fileReliabilitySERSoft error rateHardeningIntegrated controlNanotechnologyRadiation hardeningCritical elementsFault-tolerant architecturesNarrow widthProcessor pipelinesRegister filesReliability enhancementRF reliabilitySoft error rateConference Paper10.1109/DTIS.2016.7483882