Özdal, Muhammet MustafaYeşil, ŞerifKim, T.Ayupov, A.Greth, J.Burns, S.Öztürk, Özcan2018-04-122018-04-122016-06http://hdl.handle.net/11693/37725Date of Conference: 18-22 June 2016Conference name: ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) 2016Specialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable architecture template that is specifically optimized for iterative vertex-centric graph applications with irregular access patterns and asymmetric convergence. The proposed architecture addresses the limitations of the existing multi-core CPU and GPU architectures for these types of applications. The SystemC-based template we provide can be customized easily for different vertex-centric applications by inserting application-level data structures and functions. After that, a cycle-accurate simulator and RTL can be generated to model the target hardware accelerators. In our experiments, we study several graph-parallel applications, and show that the hardware accelerators generated by our template can outperform a 24 core high end server CPU system by up to 3x in terms of performance. We also estimate the area requirement and power consumption of these hardware accelerators through physical-aware logic synthesis, and show up to 65x better power consumption with significantly smaller area. © 2016 IEEE.EnglishHardwareInstruction setsGraphics processing unitsData structuresBandwidthConvergenceC++ languageComputer architectureData structuresGraph grammarsHigh level synthesisMicroprocessor chipsMultiprocessing systemsOptimisationPower aware computingConference Paper10.1109/ISCA.2016.24