Demirbas, D.Akturk, I.Ozturk, O.Güdükbay, Uğur2016-02-082016-02-0820140010-4620http://hdl.handle.net/11693/26583As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in application-specific NoC design is to find the right balance among different tradeoffs, such as communication latency, power consumption and chip area. We propose a novel approach that generates latency-aware heterogeneous NoC topology. Experimental results show that our approach improves the total communication latency up to 27% with modest power consumption. © 2013 The Author 2013. Published by Oxford University Press on behalf of The British Computer Society.EnglishMany-core architecturesMultiprocessor system-on-chip designNetwork-on-chip synthesisComputer architectureHeterogeneous networksMicroprocessor chipsMultiprocessing systemsRoutersVLSI circuitsChip multiprocessorCommunication latencyHeterogeneous NoCArticle10.1093/comjnl/bxt011