Aktürk, İsmailÖztürk, Özcan2016-02-082016-02-082013-02-03http://hdl.handle.net/11693/28014Date of Conference: 27 Feb.-1 March 2013Conference name: 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013Network-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. We explore how heterogeneous processors can be mapped onto the given 3D chip area to minimize the data access costs. Our initial results indicate that the proposed approach generates promising results within tolerable solution times. © 2013 IEEE.English3DChip multiprocessorHeterogeneousNoCCommunication reductionHeterogeneousHeterogeneous processorsNetwork-on-chip architecturesThree dimensional integrated circuitsMicroprocessor chipsRoutersVLSI circuitsThree dimensional computer graphicsConference Paper10.1109/PDP.2013.83