Instruction-level reliability improvement for embedded systems

Simple item page
dc.contributor.authorTekgül, Hakanen_US
dc.contributor.authorÖztürk, Özcanen_US
dc.contributor.bilkentauthorTekgül, Hakan
dc.contributor.bilkentauthorÖztürk, Özcan
dc.coverage.spatialHammamet, Tunisiaen_US
dc.date.accessioned2021-02-05T06:17:00Z
dc.date.available2021-02-05T06:17:00Z
dc.date.issued2020-09
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 7-10 June 2020en_US
dc.descriptionConference name: 2020 IEEE International Conference on Design and Test of Integrated Micro and Nano-Systems, DTS 2020en_US
dc.description.abstractWith the increasing number of applications in embedded computing systems, it became indispensable for the system designers to consider multiple objectives including power, performance, and reliability. Among these, reliability is a bigger constraint for safety critical applications. For example, fault tolerance of transportation systems has become very critical with the use of many embedded on-board devices. There are many techniques proposed in the past decade to increase the fault tolerance of such systems. However, many of these techniques come with a significant overhead, which make them infeasible in most of the embedded execution scenarios. Motivated by this observation, our main contribution in this paper is to propose and evaluate an instruction criticality based reliable source code generation algorithm. Specifically, we propose an instruction ranking formula based on our detailed fault injection experiments. We use instruction rankings along with the overhead tolerance limits and generate a source code with increased fault tolerance. The primary goal behind this work is to improve reliability of an application while keeping the performance effects minimal. We apply state-of-the-art reliability techniques to evaluate our approach on a set of benchmarks. Our experimental results show that, the proposed approach achieves up to 8% decrease in error rates with only 10% performance overhead. The error rates further decrease with higher overhead tolerances.en_US
dc.identifier.doi10.1109/DTS48731.2020.9196195en_US
dc.identifier.isbn9781728154282
dc.identifier.urihttp://hdl.handle.net/11693/55004
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttps://doi.org/10.1109/DTS48731.2020.9196195en_US
dc.source.title2020 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)en_US
dc.subjectFault toleranceen_US
dc.subjectReliabilityen_US
dc.subjectInstruction criticalityen_US
dc.subjectEmbedded systemsen_US
dc.titleInstruction-level reliability improvement for embedded systemsen_US
dc.typeConference Paperen_US
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
Instruction-level_reliability_improvement_for_embedded_systems.pdf
Size:
412.65 KB
Format:
Adobe Portable Document Format
Description:
Download
License bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.71 KB
Format:
Item-specific license agreed upon to submission
Description:
Download
Collections
Department of Computer Engineering