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dc.contributor.authorEl-Atab, N.en_US
dc.contributor.authorOkyay, A. K.en_US
dc.contributor.authorNayfeh, A.en_US
dc.date.accessioned2018-04-12T13:54:06Z
dc.date.available2018-04-12T13:54:06Z
dc.date.issued2016en_US
dc.identifier.isbn9783319204819
dc.identifier.isbn9783319204802
dc.identifier.urihttp://hdl.handle.net/11693/38363
dc.description.abstractCurrent flash memory devices are expected to face two major challenges in the near future: density and voltage scaling. The density of the memory is related to the gate length scaling which is constrained by the gate stack, namely, the tunnel oxide thickness. In fact, the gate length is required to be commensurate with the gate stack in order to maintain a good gate control and to avoid short channel effects. However, in conventional flash memories, the tunnel oxide thickness has a lower limit of 6-7 nm (depending on NOR or NAND structure) in order to avoid back-tunneling and thus leakage of charges which destroys the necessary retention characteristic of the memory (>10 years). The second problem which needs to be solved is the high program and erase operating voltages. Once again, the limitation to operating voltage scaling is the inability to reduce gate stack thickness. Therefore, it is imperative to find novel structures and materials to be incorporated in the memory cells which would allow tunnel oxide and voltage scaling. In this study, MOSFET- and MOSCAP-based memory devices are investigated along with the use of 2-nm silicon nanoparticles (Si-NPs) for charge storage. Atomic layer deposition is used to deposit the active layer of the memory and the spin coating is performed to deliver the Si-nanoparticles across the sample.en_US
dc.language.isoEnglishen_US
dc.source.title3D Stacked Chips: From Emerging Processes to Heterogeneous Systemsen_US
dc.relation.isversionofhttp://dx.doi.org/10.1007/978-3-319-20481-9_7en_US
dc.subjectAtomic layer depositionen_US
dc.subjectField effect transistorsen_US
dc.subjectLogic gatesen_US
dc.subjectMOS devicesen_US
dc.subjectMOSFET devicesen_US
dc.subjectNanoparticlesen_US
dc.subjectSiliconen_US
dc.subjectStatic random access storageen_US
dc.subjectSynthesis (chemical)en_US
dc.subjectVoltage scalingen_US
dc.subjectGate length scalingen_US
dc.subjectLow-power memoryen_US
dc.subjectOperating voltageen_US
dc.subjectProgram and eraseen_US
dc.subjectRetention characteristicsen_US
dc.subjectShort-channel effecten_US
dc.subjectSilicon nanoparticlesen_US
dc.subjectTunnel oxide thicknessen_US
dc.subjectFlash memoryen_US
dc.titleTwo-nanometer laser synthesized Si-nanoparticles for low power memory applicationsen_US
dc.typeBook Chapteren_US
dc.departmentUNAM - Institute of Materials Science and Nanotechnology
dc.citation.spage129en_US
dc.citation.epage156en_US
dc.identifier.doi10.1007/978-3-319-20481-9_7en_US
dc.publisherSpringer International Publishingen_US


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