An fpga implementation of successive cancellation list decoding for polar codes
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Polar Codes are the rst asymptotically provably capacity achieving error correction codes under low complexity successive cancellation (SC) decoding for binary discrete memoryless symmetric channels. Although SC is a low complexity algorithm, it does not provide as good performance as a maximum-likelihood (ML) decoder, unless su ciently large code block is used. SC is a soft decision decoding algorithm such that it employs depth- rst searching method with a divide and conquer approach to nd a su ciently perfect estimate of decision vector. Using SC with a list (SCL) improves the performance of SC decoder such that it provides near ML performance. SCL decoder employs beam search method as a greedy algorithm to achieve ML performance without considering all possible codewords. The ML performance of polar codes is not good enough due to the minimum hamming distance of possible codewords. For the purpose of increasing the minimum distance, cyclic redundancy check aided (CRC-SCL) decoding algorithm can be used. This algorithm makes polar codes competitive with state of the art codes by exchanging complexity with performance. In this thesis, we present an FPGA implementation of an adaptive list decoder; consisting of SC, SCL and CRC decoders to meet with the tradeo between performance and complexity.