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dc.contributor.authorYemliha, T.en_US
dc.contributor.authorKandemir, M.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.contributor.authorKultursay, E.en_US
dc.contributor.authorMuralidhara, S. P.en_US
dc.coverage.spatialIschia, Italy
dc.date.accessioned2016-02-08T12:22:29Z
dc.date.available2016-02-08T12:22:29Z
dc.date.issued2010-08-09en_US
dc.identifier.issn0302-9743
dc.identifier.urihttp://hdl.handle.net/11693/28506
dc.descriptionDate of Conference: 31 August - 3 September, 2010
dc.descriptionConference name: Euro-Par: 16th European Conference on Parallel Processing - International Euro-Par Conference
dc.description.abstractAs chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. Unfortunately, most of the published work in the literature focuses only on one of these problems, and this can prevent one from achieving the best possible performance. The main goal of this paper is to propose and evaluate a compiler-directed code parallelization scheme, which considers both parallelism and data locality at the same time. Our compiler captures the inherent parallelism and data reuse in the application code being analyzed using a novel representation called the locality-parallelism graph (LPG). Our partitioning/scheduling algorithm assigns the nodes of this graph to the processors in the architecture and schedules them for execution. We implemented this algorithm and evaluated its effectiveness using a set of benchmark codes. The results collected so far indicate that our approach improves overall execution latency significantly. In this paper, we also introduce an ILP (Integer Linear Programming) based formulation of the problem, and implement the schedule obtained by the ILP solver. The results indicate that our approach gets within 4% of the ILP solution. © 2010 Springer-Verlag.en_US
dc.language.isoEnglishen_US
dc.source.titleEuro-Par 2010 - Parallel Processing -16th International Euro-Par Conferenceen_US
dc.relation.isversionofhttps://doi.org/10.1007/978-3-642-15277-1_20en_US
dc.subjectApplication codesen_US
dc.subjectBenchmark codesen_US
dc.subjectChip multiprocessoren_US
dc.subjectCode schedulingen_US
dc.subjectCritical issuesen_US
dc.subjectData localityen_US
dc.subjectData reuseen_US
dc.subjectInherent parallelismen_US
dc.subjectInteger linear programmingen_US
dc.subjectOverall executionen_US
dc.subjectParallelizationsen_US
dc.subjectProgramming supporten_US
dc.subjectComputer architectureen_US
dc.subjectInteger programmingen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectOptimizationen_US
dc.subjectProgram compilersen_US
dc.subjectSystems analysisen_US
dc.subjectMultiprocessing systemsen_US
dc.titleCode scheduling for optimizing parallelism and data localityen_US
dc.typeConference Paperen_US
dc.departmentDepartment of Computer Engineeringen_US
dc.citation.spage204en_US
dc.citation.epage216en_US
dc.identifier.doi10.1007/978-3-642-15277-1_20en_US
dc.publisherSpringeren_US


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