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dc.contributor.authorOzaktas, H. M.en_US
dc.contributor.authorGoodman, J. W.en_US
dc.date.accessioned2016-02-08T10:54:21Z
dc.date.available2016-02-08T10:54:21Z
dc.date.issued1993en_US
dc.identifier.issn0020-7217
dc.identifier.urihttp://hdl.handle.net/11693/26054
dc.description.abstractBased on idealized interconnect scaling rules, we derive the optimal distribution of linewidths as a function of length for wire-limited layouts utilizing RC-limited interconnections. We show that the width of the wires should be chosen proportional to the cube root of their length for two-dimensional layouts and proportional to the fourth root of their length for full three-dimensional layouts so as to minimize average signal delay.en_US
dc.language.isoEnglishen_US
dc.source.titleInternational Journal of Electronicsen_US
dc.relation.isversionofhttp://dx.doi.org/10.1080/00207219308925844en_US
dc.subjectElectric delay linesen_US
dc.subjectElectric wiringen_US
dc.subjectElectronics packagingen_US
dc.subjectGeometryen_US
dc.subjectMathematical modelsen_US
dc.subjectOptimizationen_US
dc.subjectThree dimensionalen_US
dc.subjectAverage signal delayen_US
dc.subjectInterconnect scaling rulesen_US
dc.subjectOptimal linewidth distributionen_US
dc.subjectResistor capacitor (RC) limited circuitsen_US
dc.subjectIntegrated circuit layouten_US
dc.titleOptimal linewidth distribution minimizing average signal delay for RC limited circuitsen_US
dc.typeArticleen_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.citation.spage407en_US
dc.citation.epage410en_US
dc.citation.volumeNumber74en_US
dc.citation.issueNumber3en_US
dc.identifier.doi10.1080/00207219308925844en_US
dc.publisherTaylor & Francisen_US


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