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      Fault-tolerant topology generation method for application-specific network-on-chips

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      Author
      Tosun, S.
      Ajabshir, V. B.
      Mercanoglu, O.
      Ozturk, O.
      Date
      2015
      Source Title
      IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems
      Print ISSN
      0278-0070
      Electronic ISSN
      1937-4151
      Publisher
      Institute of Electrical and Electronics Engineers
      Volume
      34
      Issue
      9
      Pages
      1495 - 1508
      Language
      English
      Type
      Article
      Item Usage Stats
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      119
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      Abstract
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.
      Keywords
      Energy minimization
      Benchmarking
      Conformal mapping
      Design
      Distributed computer systems
      Energy utilization
      Fault tolerance
      Fault tolerant computer systems
      Mapping
      Microprocessor chips
      Routers
      Servers
      Simulated annealing
      Topology
      VLSI circuits
      Application specific
      Application specific network on chip
      Energy minimization
      Integrated circuits (ICs)
      Multimedia benchmarks
      Network-on-chip (NoC)
      Topology design
      Total energy consumption
      Permalink
      http://hdl.handle.net/11693/21114
      Published Version (Please cite this version)
      http://dx.doi.org/10.1109/TCAD.2015.2413848
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