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dc.contributor.advisorDana, Aykutluen_US
dc.contributor.authorKocaay, Denizen_US
dc.date.accessioned2016-01-08T20:03:29Z
dc.date.available2016-01-08T20:03:29Z
dc.date.issued2013
dc.identifier.urihttp://hdl.handle.net/11693/16930
dc.descriptionAnkara : Materials Science and Nanotechnology Program of the Graduate School of Engineering and Science of Bilkent Univerity, 2013.en_US
dc.descriptionThesis (Master's) -- Bilkent University, 2013.en_US
dc.descriptionIncludes bibliographical references leaves 87-98.en_US
dc.description.abstractWith the ongoing development in portable electronic devices, low power consumption, improved data retention rate and higher operation speed are the merits demanded by modern non-volatile memory technology. Flash memory devices with discrete charge-trapping media are regarded as an alternative solution to conventional floating gate technology. Flash memories utilizing Sinitride as charge storage media dominate due to enhanced endurance, better scaling capability and simple fabrication. The use of high-k dielectrics as tunnel layer and control layer is also crucial in charge-trap flash memory devices since they allow further scaling and enhanced charge injection without data retention degradation. Atomic layer deposition (ALD) is a powerful technique for the growth of pinhole-free high-k dielectrics with precisely controlled thickness and high conformality. The application of graphene as charge trapping medium in flash memory devices is promising to obtain improved charge storage capability with miniaturization. Graphene acts as an effective charge storage medium due to high density of states in deep energy levels. In this thesis, we fabricate graphene flash memory devices with ALD-grown HfO2/AlN as tunnel layer and Al2O3 as control layer. Graphene oxide nanosheets are derived from the acid exfoliation of natural graphite by Hummers Method. The graphene layer is obtained by spin-coating of water soluble graphene oxide suspension followed by a thermal annealing process. Memory performance including hysteresis window, data retention rate and program transient characteristics for both electron and hole storage mechanisms are determined by performing high frequency capacitance-voltage measurements. For comparing the memory effect of graphene on device performance, we also fabricate and characterize identical flash capacitors with Si-rich SiN layer as charge storage medium and HfO2 as tunnel oxide layer. The Si-nitride films are deposited with high SiH4/NH3 gas flow ratio by plasma-enhanced chemical vapor deposition system. Graphene flash memory devices exhibit superior memory performance. Compared with Si-nitride based cells, hysteresis window, retention performance and programming speed are both significantly enhanced with the use of graphene. For electron storage, graphene flash memory provides a saturated flat band shift of 1.2 V at a write-pulse duration of 100 ns with a voltage bias of 5 V. The high density of states and high work function of graphene improve the memory performance, leading to increased charge storage capability, enhanced retention rate and faster programming operation at low voltages. The use of graphene as charge storage medium and ALD-grown high-k dielectrics as tunnel and control layers improves the existing flash technology and satisfies the requirements including scalability, at least 10-year retention, low voltage operation, faster write performance and CMOS-compatible fabrication.en_US
dc.description.statementofresponsibilityKocaay, Denizen_US
dc.format.extentxiv, 98 leaves, graphicsen_US
dc.language.isoEnglishen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectFlash memoryen_US
dc.subjectgrapheneen_US
dc.subjecthigh-k dielectricsen_US
dc.subjectALDen_US
dc.subject.lccTK7895.M4 K63 2013en_US
dc.subject.lcshFlash memories (Computers)en_US
dc.subject.lcshGate array circuits.en_US
dc.subject.lcshAtomic layer deposition.en_US
dc.subject.lcshGraphite.en_US
dc.titleHigh performance floating gate memories using graphene as charge storage medium and atomic layer deposited high-k dielectric layers as tunnel barrieren_US
dc.typeThesisen_US
dc.departmentGraduate Program in Materials Science and Nanotechnologyen_US
dc.publisherBilkent Universityen_US
dc.description.degreeM.S.en_US


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