Application-specific heterogeneous network-on-chip design
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With increasing communication demands of processors and memory cores in Systems-on-Chips (SoCs), application-specific and scalable Network-on-Chips (NoCs) are emerged to interconnect processing cores and subsystems in Multiprocessor System-on-Chips (MPSoCs). The challenge of application-specific NoC design is to find the right balance among different trade-offs such as communication latency, power consumption, and chip area. This thesis introduces a novel heterogeneous NoC design approach where biologically inspired evolutionary algorithm and 2-dimensional rectangle packing algorithm are used to place the processing elements with various properties into a constrained NoC area according to the tasks generated by Task Graph for Free (TGFF). TGFF is one of the pseudo-random task graph generators used for scheduling and allocation. Based on a given task graph, we minimize the maximum execution time in a Heterogeneous Chip-Multiprocessor. We specifi- cally emphasize on the communication cost as it is a big overhead in a multi-core architecture. Experimental results show that our approach improves total communication latency up to 27% with modest power consumption.
KeywordsNetwork-on-Chip (NoC) synthesis
Multiprocessor-System-on-Chip (MPSoC) design