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Fault-tolerant irregular topology design method for network-on-chips
(IEEE, 2014)
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...
Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect
(IEEE, 2013)
Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this ...
Improving multicore system performance through data compression
(Wiley, 2017)
As applications become more and more complex, it is becoming extremely important to have sufficient compute power on the chip. Multicore and many-core systems have been introduced to address this problem. This chapter ...
A scratch-pad memory aware dynamic loop scheduling algorithm
(IEEE, 2008-03)
Executing array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, ...
SPM management using markov chain based data access prediction
(IEEE, 2008-11)
Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular accesses like scalar values and array expressions ...
Adaptive compute-phase prediction and thread prioritization to mitigate memory access latency
(ACM, 2014-06)
The full potential of chip multiprocessors remains unex- ploited due to the thread oblivious memory access sched- ulers used in off-chip main memory controllers. This is especially pronounced in embedded systems due to ...
Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table
(ACM, 2016- 05)
Chip multiprocessors (CMPs) require effective cache coher-ence protocols as well as fast virtual-To-physical address trans-lation mechanisms for high performance. Directory-based cache coherence protocols are the ...
Cache hierarchy-aware query mapping on emerging multicore architectures
(IEEE, 2017)
One of the important characteristics of emerging multicores/manycores is the existence of 'shared on-chip caches,' through which different threads/processes can share data (help each other) or displace each other's data ...
FPGA implementation of a fault-tolerant application-specific NoC design
(IEEE, 2016-04)
Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem ...
Register file reliability enhancement through adjacent narrow-width exploitation
(IEEE, 2016-04)
Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor ...