Limit to bit rate capacity of electrical interconnects from aspect ratio of system architecture
Miller, D. A. B.
Ozaktas, H. M.
Journal of Parallel and Distributed Computing
Miller, D. A. B., & Ozaktas, H. M. (1997). Limit to the bit-rate capacity of electrical interconnects from the aspect ratio of the system architecture. Journal of parallel and distributed computing, 41(1), 42-52.
Please cite this item using this persistent URLhttp://hdl.handle.net/11693/10863
We show that there is a limit to the total number of bits per second, B, of information that can flow in a simple digital electrical interconnection that is set only by the ratio of the length l of the interconnection to the total cross-sectional dimension p A of the interconnect wiring—the “aspect ratio” of the interconnection. This limit is largely independent of the details of the design of the electrical lines. The limit is approximately B BoA/l2 bits/s, with Bo 1015 (bit/s) for high-performance strip lines and cables, 1016 for small on-chip lines, and 1017–1018 for equalized lines. Because the limit is scale-invariant, neither growing nor shrinking the system substantially changes the limit. Exceeding this limit requires techniques such as repeatering, coding, and multilevel modulation. Such a limit will become a problem as machines approach Tb/s information bandwidths. The limit will particularly affect architectures in which one processor must talk reasonably directly with many others. We argue that optical interconnects can solve this problem since they avoid the resistive loss physics that gives this limit. © 1997 Academic Press