Now showing items 1-4 of 4
Code scheduling for optimizing parallelism and data locality
As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. ...
An ILP formulation for application mapping onto Network-on-Chips
Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems ...
Optimizing shared cache behavior of chip multiprocessors
One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work ...
Slicing based code parallelization for minimizing inter-processor communication
One of the critical problems in distributed memory multi-core architectures is scalable parallelization that minimizes inter-processor communication. Using the concept of iteration space slicing, this paper presents a new ...