Now showing items 1-17 of 17

    • Adaptive routing framework for network on chip architectures 

      Mustafa, N. U.; Ozturk, O.; Niar, S. (Association for Computing Machinery, 2016)
      In this paper we suggest and demonstrate the idea of applying multiple routing algorithms during the execution of a real application mapped on a Network-on-Chip (NoC). Traffic pattern of a real application may change during ...
    • Analog CMOS implementation of cellular neural networks 

      Baktır, I. A.; Tan, M. A. (IEEE, 1993)
      The analog CMOS circuit realization of cellular neural networks with transconductance elements is presented. This realization can be easily adapted to various types of applications in image processing just by choosing the ...
    • Analysis of Lagrangian lower bounds for a graph partitioning problem 

      Adil, G. K.; Ghosh, J. B. (Institute for Operations Research and the Management Sciences (INFORMS), 1999)
      Recently, Ahmadi and Tang (1991) demonstrated how various manufacturing problems can be modeled and solved as graph partitioning problems. They use Lagrangian relaxation of two different mixed integer programming formulations ...
    • Application-specific heterogeneous network-on-chip design 

      Demirbas, D.; Akturk, I.; Ozturk, O.; Güdükbay U. (Oxford University Press, 2014)
      As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in ...
    • Circuit theoretical method for efficient finite element analysis of acoustical problems 

      Ekinci, A. S.; Atalar, Abdullah (IEEE, 1998)
      In the last decade, there has been an outstanding improvement in the computer aided design tools for VLSI circuits regarding solution times and the circuit complexity. This study proposes formulating the acoustic field ...
    • Energy reduction in 3D NoCs through communication optimization 

      Ozturk, O.; Akturk I.; Kadayif I.; Tosun, S. (Springer Wien, 2015)
      Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining ...
    • Fault-tolerant irregular topology design method for network-on-chips 

      Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2014)
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...
    • Fault-tolerant topology generation method for application-specific network-on-chips 

      Tosun, S.; Ajabshir, V. B.; Mercanoglu, O.; Ozturk, O. (Institute of Electrical and Electronics Engineers, 2015)
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...
    • Heterogeneous network-on-chip design through evolutionary computing 

      Ozturk, O.; Demirbas, D. (Taylor & Francis, 2010)
      This article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor ...
    • An ILP formulation for application mapping onto Network-on-Chips 

      Tosun, S.; Ozturk O.; Ozen, M. (2009)
      Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems ...
    • ILP-based communication reduction for heterogeneous 3D network-on-chips 

      Akturk, I.; Ozturk, O. (IEEE, 2013)
      Network-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. ...
    • OptMem: dark-silicon aware low latency hybrid memory design 

      Onsori, S.; Asad, A.; Raahemifar, K.; Fathy, M. (Institute of Electrical and Electronics Engineers Inc., 2016)
      In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static ...
    • Plasmonic gratings for enhanced near infrared sensitivity of Silicon based Schottky photodetectors 

      Polat, K.G.; Aygun L.E.; Okyay, A., K. (2011)
      Schottky photodetectors have been intensively investigated due to their high speeds, low device capacitances, and sensitivity in telecommunication standard bands, in the 0.8μm to 1.5μm wavelength range. Due to extreme cost ...
    • Reconfigurable hardened latch and flip-flop for FPGAs 

      Ahangari, H.; Alouani, I.; Ozturk, O.; Niar, S. (IEEE Computer Society, 2017)
      In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices ...
    • VLSI circuits for adaptive digital beamforming in ultrasound imaging 

      Karaman, M.; Atalar, Abdullah; Köymen, H. (IEEE, 1993)
      For phased-array ultrasound imaging, alternative beamforming techniques and their VLSI circuits are studied to form a fully digital receive front-end hardware. In order to increase the timing accuracy in beamforming, a ...
    • Voltage island based heterogeneous NoC design through constraint programming 

      Demiriz, A.; Bagherzadeh, N.; Ozturk, O. (Pergamon Press, 2014)
      This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior ...
    • A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC 

      Ungan I.E.; Aşkar, M. (1997)
      A wired-AND current-mode logic (WCML) circuit technique in CMOS technology for low-voltage and high-speed VLSI circuits is proposed, and a WCML cell library is developed using standard 0.8 micron CMOS process. The proposed ...