Now showing items 1-6 of 6

    • Application mapping algorithms for mesh-based network-on-chip architectures 

      Tosun, S.; Ozturk, O.; Ozkan, E.; Ozen, M. (Springer New York LLC, 2015-03)
      Due to shrinking technology sizes, more and more processing elements and memory blocks are being integrated on a single die. However, traditional communication infrastructures (e.g., bus or point-to-point) cannot handle ...
    • Compiler directed network-on-chip reliability enhancement for chip multiprocessors 

      Ozturk, O.; Kandemir, M.; Irwin, M. J.; Narayanan, S.H. K. (Association for Computing Machinery, 2010-04)
      Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, programming them is even more challenging. As the ...
    • Dynamic thread and data mapping for NoC based CMPs 

      Kandemir, M.; Ozturk O.; Muralidhara, S.P. (2009)
      Thread mapping and data mapping are two important problems in the context of NoC (network-on-chip) based CMPs (chip multiprocessors). While a compiler can determine suitable mappings for data and threads, such static ...
    • Energy reduction in 3D NoCs through communication optimization 

      Ozturk, O.; Akturk I.; Kadayif I.; Tosun, S. (Springer Wien, 2015)
      Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining ...
    • Heterogeneous network-on-chip design through evolutionary computing 

      Ozturk, O.; Demirbas, D. (Taylor & Francis, 2010)
      This article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor ...
    • ILP-based communication reduction for heterogeneous 3D network-on-chips 

      Akturk, I.; Ozturk, O. (IEEE, 2013)
      Network-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. ...