Now showing items 1-18 of 18

    • Adaptive prefetching for shared cache based chip multiprocessors 

      Kandemir, M.; Zhang, Y.; Ozturk O. (2009)
      Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based CMP, multiple cores compete for the shared on-chip ...
    • Application-specific heterogeneous network-on-chip design 

      Demirbas, D.; Akturk, I.; Ozturk, O.; Güdükbay U. (Oxford University Press, 2014)
      As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in ...
    • Code scheduling for optimizing parallelism and data locality 

      Yemliha, T.; Kandemir, M.; Ozturk, O.; Kultursay, E.; Muralidhara, S. P. (Springer, 2010)
      As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. ...
    • An efficient computation model for coarse grained reconfigurable architectures and its applications to a reconfigurable computer 

      Atak O.; Atalar, Abdullah (2010)
      The mapping of high level applications onto the coarse grained reconfigurable architectures (CGRA) are usually performed manually by using graphical tools or when automatic compilation is used, some restrictions are imposed ...
    • Fault-tolerant irregular topology design method for network-on-chips 

      Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2014)
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...
    • Fault-tolerant topology generation method for application-specific network-on-chips 

      Tosun, S.; Ajabshir, V. B.; Mercanoglu, O.; Ozturk, O. (Institute of Electrical and Electronics Engineers, 2015)
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...
    • Heterogeneous network-on-chip design through evolutionary computing 

      Ozturk, O.; Demirbas, D. (Taylor & Francis, 2010)
      This article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor ...
    • An ILP formulation for application mapping onto Network-on-Chips 

      Tosun, S.; Ozturk O.; Ozen, M. (2009)
      Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems ...
    • ILP-based communication reduction for heterogeneous 3D network-on-chips 

      Akturk, I.; Ozturk, O. (IEEE, 2013)
      Network-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. ...
    • LoC sensor array platform for real-time coagulation measurements 

      Cakmak, O.; Kilinc, N.; Ermek, E.; Mostafazadeh, A.; Elbuken, C.; Yaralioglu, G. G.; Urey, H. (Institute of Electrical and Electronics Engineers, 2014)
      This paper reports a MEMS-based sensor array enabling multiple clot-time tests in one disposable microfluidic cartridge using plasma. The versatile LoC (Lab-on-Chip) platform technology is demonstrated here for real-time ...
    • Low power UWB transceiver design using dynamic voltage scaling 

      Garg, R.; Chunjie, D.; Jinyun, Z.; Gezici, S. (2007)
      Low power consumption is a critical issue in many UWB systems. In this paper, we investigate the application of dynamic voltage scaling (DVS) and other low power design techniques to a multiband-OFDM UWB transceiver baseband ...
    • Multicore education through simulation 

      Ozturk, O. (IEEE, 2009)
      This paper presents the experiences using a commercial full system simulation platform - Simics - in a graduate Chip Multiprocessors class. The Simics platform enables students and researchers to do research on computer ...
    • On-chip memory space partitioning for chip multiprocessors using polyhedral algebra 

      Ozturk, O.; Kandemir, M.; Irwin, M. J. (The Institution of Engineering and Technology, 2010)
      One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the ...
    • Optimizing shared cache behavior of chip multiprocessors 

      Kandemir, M.; Muralidhara, S.P.; Narayanan, S.H.K.; Zhang, Y.; Ozturk O. (2009)
      One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single processor centric data locality optimization schemes may not work ...
    • Process variation aware thread mapping for chip multiprocessors 

      Hong, S.; Narayanan, S.H.K.; Kandemir, M.; Özturk Ö. (2009)
      With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that ...
    • A scratch-pad memory aware dynamic loop scheduling algorithm 

      Ozturk O.; Kandemir, M.; Narayanan, S.H.K. (2008)
      Executing array based applications on a chip multiprocessor requires effective loop parallelization techniques. One of the critical issues that need to be tackled by an optimizing compiler in this context is loop scheduling, ...
    • Shared scratch pad memory space management across applications 

      Ozturk, Ozcan; Kandemir, M.; Son, S. W.; Kolcu, I. (Inderscience Publishers, 2009)
      Scratch Pad Memories (SPMs) have received considerable attention lately as on-chip memory building blocks. The main characteristic that distinguishes an SPM from a conventional cache memory is that the data flow is controlled ...
    • Using data compression for increasing memory system utilization 

      Ozturk, O.; Kandemir, M.; Irwin, M. J. (Institute of Electrical and Electronics Engineers, 2009-06)
      The memory system presents one of the critical challenges in embedded system design and optimization. This is mainly due to the ever-increasing code complexity of embedded applications and the exponential increase seen in ...