Browsing by Keywords "Field programmable gate arrays (FPGA)"
Now showing items 1-7 of 7
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Autofocus method in thermal cameras based on image histogram
(IEEE, 2011)In this paper, a new histogram based auto-focusing method for thermal cameras is proposed. This proposed method is realized by FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) working together and ... -
Fiber laser-microscope system for femtosecond photodisruption of biological samples
(Optical Society of America, 2012-02-22)We report on the development of a ultrafast fiber lasermicroscope system for femtosecond photodisruption of biological targets. A mode-locked Yb-fiber laser oscillator generates few-nJ pulses at 32.7 MHz repetition rate, ... -
An FPGA implementation architecture for decoding of polar codes
(IEEE, 2011)Polar codes are a class of codes versatile enough to achieve the Shannon bound in a large array of source and channel coding problems. For that reason it is important to have efficient implementation architectures for polar ... -
FPGA implementation of a fault-tolerant application-specific NoC design
(IEEE, 2016-04)Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem ... -
JPEG hardware accelerator design for FPGA
(IEEE, 2007)A fully pipelined JPEG hardware accelerator that runs on FPGA is presented. The accelerator is designed interactively in a simulation environment, using a DSP hardware design automation tool chain. The encoder part of the ... -
Proof-of-concept energy-efficient and real-time hemodynamic feature extraction from bioimpedance signals using a mixed-signal field programmable analog array
(IEEE, 2017)We present a mixed-signal system for extracting hemodynamic parameters in real-time from noisy electrical bioimpedance (EBI) measurements in an energy-efficient manner. The proof-of-concept system consists of floating-gate-based ... -
Reconfigurable hardened latch and flip-flop for FPGAs
(IEEE, 2017-07)In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices ...
