Now showing items 1-2 of 2

    • Fault-tolerant irregular topology design method for network-on-chips 

      Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2014)
      As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, ...
    • FPGA implementation of a fault-tolerant application-specific NoC design 

      Yesil, S.; Tosun, S.; Ozturk, O. (Institute of Electrical and Electronics Engineers Inc., 2016)
      Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem ...