Now showing items 1-7 of 7

    • Adaptive compute-phase prediction and thread prioritization to mitigate memory access latency 

      Aktürk, İsmail; Öztürk, Özcan (ACM, 2014-06)
      The full potential of chip multiprocessors remains unex- ploited due to the thread oblivious memory access sched- ulers used in off-chip main memory controllers. This is especially pronounced in embedded systems due to ...
    • Application-specific heterogeneous network-on-chip design 

      Demirbas, D.; Akturk, I.; Ozturk, O.; Güdükbay U. (Oxford University Press, 2014)
      As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in ...
    • Code scheduling for optimizing parallelism and data locality 

      Yemliha, T.; Kandemir, M.; Öztürk, Özcan; Kultursay, E.; Muralidhara, S. P. (Springer, 2010-08-09)
      As chip multiprocessors proliferate, programming support for these devices is likely to receive a lot of attention in the near future. Parallelism and data locality are two critical issues in a chip multiprocessor environment. ...
    • Heterogeneous network-on-chip design through evolutionary computing 

      Ozturk, O.; Demirbas, D. (Taylor & Francis, 2010)
      This article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor ...
    • ILP-based communication reduction for heterogeneous 3D network-on-chips 

      Aktürk, İsmail; Öztürk, Özcan (IEEE, 2013-02-03)
      Network-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. ...
    • On-chip memory space partitioning for chip multiprocessors using polyhedral algebra 

      Ozturk, O.; Kandemir, M.; Irwin, M. J. (The Institution of Engineering and Technology, 2010)
      One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the ...
    • Shared scratch pad memory space management across applications 

      Ozturk, Ozcan; Kandemir, M.; Son, S. W.; Kolcu, I. (Inderscience Publishers, 2009)
      Scratch Pad Memories (SPMs) have received considerable attention lately as on-chip memory building blocks. The main characteristic that distinguishes an SPM from a conventional cache memory is that the data flow is controlled ...