Browsing by Keywords "Address translation"
Now showing items 1-2 of 2
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Classifying data blocks at subpage granularity with an on-chip page table to improve coherence in tiled CMPs
(Institute of Electrical and Electronics Engineers, 2018)As shown in some prior studies, a significant percentage of data blocks accessed in parallel codes are private, and not keeping track of those blocks can improve the effectiveness of directory structures in Chip multiprocessors ... -
Hardware/software approaches for reducing the process variation impact on instruction fetches
(ACM New York, NY, 2013)As technology moves towards finer process geometries, it is becoming extremely difficult to control critical physical parameters such as channel length, gate oxide thickness, and dopant ion concentration. Variations in ...
