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application/pdfIEEEIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018;37;4;10.1109/TCAD.2017.2729280Address translationcache coherencechip multiprocessor (CMP)directory cachepage tabletranslation look-aside buffer (TLB)Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPsMohammadreza SoltaniyehIsmail KadayifOzcan Ozturk
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems806 April 201843710.1109/TCAD.2017.2729280819
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